`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"
module 	Ctrl_gen(
    input  [3:0]  exe_type,
    output [4:0]  ctrl_bus
);
    reg    Branch;
    reg    Jump;
    reg    Reg_W;
    reg    Mem_W;
    reg    Mem_R;
    assign ctrl_bus = {
        Branch,
        Jump,
        Reg_W,
        Mem_W,
        Mem_R
    };

    always@(*) begin 
        case(exe_type)
            `EXE_TYPE_BRANCH:
                Branch=`LOGI_TRUE;
            default: 
                Branch=`LOGI_FALSE;
        endcase
    end

    always@(*) begin
        case(exe_type)
            `EXE_TYPE_JAL:
                Jump =`LOGI_TRUE;
            `EXE_TYPE_JALR:
                Jump =`LOGI_TRUE;            
            default: 
                Jump =`LOGI_FALSE;
        endcase
    end

    always@(*) begin
        case(exe_type)
            `EXE_TYPE_LOAD:
                Reg_W=`LOGI_TRUE;
            `EXE_TYPE_LUI:
                Reg_W=`LOGI_TRUE;
            `EXE_TYPE_AUIPC:
                Reg_W=`LOGI_TRUE;
            `EXE_TYPE_JAL:
                Reg_W=`LOGI_TRUE;
            `EXE_TYPE_JALR:
                Reg_W=`LOGI_TRUE;
            `EXE_TYPE_MUL:
                Reg_W=`LOGI_TRUE;
            `EXE_TYPE_DIV:
                Reg_W=`LOGI_TRUE;
            `EXE_TYPE_COMMON:
                Reg_W=`LOGI_TRUE;
            default: 
                Reg_W=`LOGI_FALSE;
        endcase
    end

    always@(*) begin
        case(exe_type)
            `EXE_TYPE_LOAD:
                Mem_R=`LOGI_TRUE;
            default: 
                Mem_R=`LOGI_FALSE;
        endcase
    end

    always@(*) begin
        case(exe_type)
            `EXE_TYPE_STORE:
                Mem_W=`LOGI_TRUE;
            default: 
                Mem_W=`LOGI_FALSE;
        endcase
    end

endmodule